1. FIELD OF THE INVENTION
This invention relates in general to semiconductor memories and, more specifically, to stress testing of such memories.
2. STATE OF THE ART
As shown in FIG. 1, a portion 10 of a conventional Dynamic Random Access Memory (DRAM) (not shown in its entirety) includes sense amplifiers 12 and 14 shared by a pair of sub-arrays 16 and 18. During some read operations within the sub-array 16, an isolation signal ISO.sub.-- 2 activates isolation NMOS transistors 20 so logic bits on bitlines 22 within the sub-array 16 can be sensed by shared sense amplifiers 12 and 14. Meanwhile, another isolation signal ISO.sub.-- 3 deactivates isolation NMOS transistors 24 so signals on bitlines 26 within the sub-array 18 do not reach the shared sense amplifiers 12 and 14 during the read operations. Of course, some read operations in the sub-array 18 are performed in a complementary manner, with the isolation NMOS transistors 24 in an activated state and the isolation NMOS transistors 20 in a deactivated state.
As described in U.S. Pat. No. 5,339,273 to Taguchi, one method for stress testing the conventional DRAM involves reading a logic bit from one of the sub-arrays 16 and 18, for example, while both the isolation NMOS transistors 20 and the isolation NMOS transistors 24 are activated. This loads a memory cell (not shown) outputting the logic bit with approximately twice the normal bitline capacitance C.sub.bitline. When the memory cell is weak, its stored charge q cannot overcome the doubled bitline capacitance C.sub.bitline to produce a voltage V.sub.sense at one of the sense amplifiers 12 and 14 that is of sufficient magnitude to be sensed (i.e., V.sub.sense =q.div.C.sub.bitline, so that when C.sub.bitline doubles and q remains constant, V.sub.sense is cut in half). As a result, the logic bit may be misread, thereby identifying the memory cell as being weak. The row or column (not shown) containing the weak memory cell can then be replaced with a redundant row or column (not shown), or the DRAM can be scrapped.
Unfortunately, the Taguchi method described above does not work with sense amplifiers 28 and 30 positioned outside the sub-arrays 16 and 18, because these amplifiers 28 and 30 are each connected to only one of the sub-arrays 16 and 18. As a result, memory cells (not shown) connected to the sense amplifiers 28 and 30 through bitlines 32 and 34 and isolating NMOS transistors 36 and 38 (activated by isolation signals ISO.sub.-- 1 and ISO.sub.-- 4) cannot be loaded with double their normal bitline capacitance, and thus cannot be stress tested, using the described Taguchi method.
Therefore, there is a need in the art for an apparatus and method in a semiconductor memory, such as a DRAM, for stress testing memory cells associated with sense amplifiers connected to only one sub-array within the memory.